The present disclosure relates to electronic design automation (EDA), and more particularly to constructing integrated circuit (IC) design intents requiring double-patterning technique (DPT) by adding fill shapes to a layer of the design intent at a DPT spacing rule.
Improvements in semiconductor process technology can increase the pattern density of shapes printed into a layer on the surface of a wafer below the minimum manufacture-able line-and-space-width, hereinafter also referred to as “minimum pitch”, that is achievable using just a single mask to pattern the layer for a given generation of photolithography printing technology. As an example, double-patterning technique or technology (DPT) has been used for manufacturing a design intent, hereinafter also referred to as “layout pattern,” “design shapes,” or “shapes,” having more than a single pitch within the spacing of a single minimum pitch that is printable by using just a single photolithographic mask. DPT uses two different masks to produce higher pattern surface density in a process layer of the design intent than is achievable by using just one mask to print that layer. However, double-patterning technology requires special design rules, EDA, and wafer processing procedures that are more complicated than standard photolithography printing technology.
Advanced process technologies use chemical mechanical polishing (CMP) techniques to flatten or “planarize” the surface of a semiconductor wafer as flat as possible during a multitude of processing steps. A flat wafer surface is desirable to obtain the wider manufacturing tolerance for depth of focus during advanced photolithographic printing as well as maintain uniform thicknesses of process layers on the wafer surface. However, the rate of CMP material removal from the wafer surface at the individual chip scale may vary in accordance with the type of materials, the distribution, and pattern density of the materials or density of material shapes per unit of polishing surface area.
For example, a soft material such as a metal may polish faster than a relatively harder material such as a dielectric material. A design intent may include a memory core region that includes a multitude of metal shapes spaced at minimum pitch resulting in a high density of metal shape per unit of surface area and may also include a region outside the memory core, hereinafter also referred to as “periphery,” that includes fewer metal shapes at a lower density of metal shape per unit of surface area relative to the memory array. Such differences in density of metal shape per unit surface area on an integrated circuit (IC) die may cause the memory core to polish faster during CMP than the periphery of the IC die, which results in a problem called “dishing.”
In this example, the dishing after CMP may cause the surface of the periphery to be higher than the surface of the array, which may reduce subsequent manufacturing margins. In some cases, the remaining metal in the array may be thinned by the dishing below reliable current handling limits for IC power and signal lines running in the array region of the design intent. The dishing problem may become worse when some regions of the design intent use DPT, which may for example, greatly increases density of metal shape per unit of surface area compared to other regions of the design intent at lower density of metal shape per unit of surface area.
One solution to lessen the dishing problem caused by CMP is to add additional shapes, hereinafter also referred to as “fill shapes,” to a layer of the design intent that are not part of the design's original electrical schematic or net-list. The fill shapes are added in order to better equalize the density of a material shape per unit of surface area across the surface of the IC die. For example, after metal lines are routed by the EDA tool, additional metal fill shapes may be added to the design intent layer by the EDA tool in places that are not used by the routing of schematic or net-list specified shapes or lines. Typically, fill shape placement has not been used in regions of the design intent requiring DPT due to the complications of combining fill shape placement that are also DPT compatible without sacrificing density of metal shape per unit surface area. For example, the memory array region of the design intent may use DPT and the fill shapes added in the periphery are placed at relatively large spacing away from the DPT shapes in the array. Further, the region with fill shapes may not be using the higher pattern density DPT design rules and suffer more dishing effects than the signal shapes that do use DPT rules in the array.
Accordingly, there is a need to enable EDA tools to add fill shapes in regions of the die that use DPT design rules in order to reduce dishing problems during CMP for advanced IC manufacturing technologies.